In conventional DRAM, each memory cell is up of a MOS transistor and a capacitor. Employment of trench capacitor structures and stacked capacitor structures has greatly progressed miniaturization of DRAM. Currently, size of each memory cell (cell size) has been reduced to the area of 2F×4F=8F2 where F is the minimum processible size. That is, the minimum processible size F has been getting smaller and smaller through some periods of generation. If the cell size is generally expressed as αF2, the coefficient α has also decreased together, and today with F=0.18 μm, α=8 has been realized.
To continue this trend regarding the cell size or chip size, it is requested to satisfy α<8 for F<18 μm and α<6 for F<13 μm. Together with further progress of micro fabrication, it is an important issue how small area each cell can be formed in. In this connection, there are various proposals toward reducing the cell size of one-transistor/one capacitor memory cells to 6F2 or 4F2. However, practical application of these proposals is not easy because of the problems such as increase of electrical interference between adjacent memory cells and difficulties in the manufacturing techniques including processing and formation of films.